Data storage devices are an important part of numerous electronic devices such as computers, smart phones, digital content players (e.g., MP3 players), game consoles, control systems, and the like. Many electronic devices include non-volatile solid state memory devices, such as flash memory. One common type of flash memory device is the charge trapping (CT) NAND integrated circuit (IC). FIG. 1 shows an exemplary CT-NAND based flash memory IC. The flash memory IC 100 includes a CT-NAND memory cell array 110, control circuits 120, column decoders 130, row decoders 140, input/output (I/O) buffers 150, and the like fabricated on a monolithic semiconductor substrate. The control circuits 120, column decoders 130, row decoders 140, I/O buffers 150, and the like operate to read and write data 160 at an address 170, 175 in the memory cell array 110 in accordance with various control signals 180 received by, internal to, and/or output from the flash memory IC 100. The circuits of the flash memory IC 100 is well known in the art and therefore those aspects of the flash memory IC 100 not particular to embodiments of the present technology will not be discussed further.
Referring now to FIG. 2, an exemplary memory cell array is shown. The CT-NAND memory cell array 110 includes a plurality of CT field effect transistors (FET) 210, a plurality of drain select gates 220, a plurality of source select gates 230, a plurality of bit lines 240, a plurality of word lines 250, a plurality of drain select signal lines 260, and a plurality of source select signal lines 270. Each column of the array 110 includes a drain select gate 220, a plurality of CT-FETs 210, and a source select gate 230 serially connected source to drain between a corresponding bit line 240 and a ground potential 280. The gates of each of a plurality of CT-FETs 210 in each row of the array 110 are coupled to a corresponding word line 250. The gate of each drain select gate 220 is connected to a corresponding drain select signal line 260. The gate of each source select gate 230 is connected to a corresponding drain select signal line 270. In one implementation, the CT-FETs may be silicon-oxide-nitride-oxide-silicon (SONOS) FETs or the like. The CT-NAND memory cell array 110 is well known in the art and therefore those aspects of the CT-NAND memory cell array 110 not particular to embodiments of the present technology will not be discussed further.
During fabrication of a CT-NAND memory cell array 110 there are variances in various processes. For example, the thickness of a deposited layer may vary from one wafer to another and from one region to another on a given wafer. Similarly, the amount of material removed by an etching process may vary from one wafer to another and from one region to another on a given wafer. Accordingly, there is a continued need for improved fabrication techniques that can compensate for process variances in one or more fabrication processes.